Key Features
Verify the 16b/18b encoding for Fixed Rate Link (FRL) Packets in both 3 and 4 lane configurations
Three (3) Lane configuration supports 3Gbps & 6Gbps data rates; four (4)Lane configurations support 6Gbps, 8Gbps, 10Gbps and 12Gbps (48Gbps aggregate)
View captured data elements graphically in Event Plot and in Data Decode Table; searching and filtering data are supported
Provides visibility into the FRL packet mapping into Character Blocks and Character Block (including FEC characters) mapping into Super Blocks
View underlying TMDS video and protocol elements data island blocks and preamble data and sync control elements (Vsync and Hsync)
Supports link training through EDID and SCDC register emulation in accordance with the sink link training states defined in the HDMI 2.1 specification
Monitor Link Training transactions in the Auxiliary Channel Analyzer (ACA)utility to show SCDC reads and writes over the DDC channel
Reports the Lane Error Counts and Reed Solomon Corrections Count in the SCDC CED registers
Deep Analysis
The 980 HDMI 2.1 Protocol Analyzer module provides the deep analysis test features necessary to test the development of your HDMI 2.1 FRL- capable source device. Deep analysis enables you to identify and resolve interoperability problems early in the product life cycle. The 980 HDMI 2.1 Protocol Analyzer depicts the incoming FRL packet structure and associated control elements. This includes depicting the Character Block structure and Super Block structure. All FRL packet data elements are assigned precise timestamps.
FPM-510
